W641GG2JB Datasheet, PDF (63/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.15.3 Write with Autoprecharge
0
1
2
3
4
5
6
7
8
9
10
CLK#
CLK
Com. WR/A
N/D
DES
DES
DES
DES
DES
DES
DES
DES
DES
A9,
A7-A2
B/C
A8
WDQS
WL = 3
tWR/A=3
tRP
DQ
D0 D1 D2 D3
WDQS
DQ
WL = 4
tRASMIN
satisifed
Begin of
Autoprecharge
tWR/A=3
tRP
D0 D1 D2 D3
tRASMIN
satisifed
Begin of
Autoprecharge
Com. : Command
Addr. : Address B / C
WL : Write Latency
Don‘t care
B / C: Bank / Column address
WR/A : WRITE with auto-precharge
D# : Data to B / C
DES : Deselect
N/D : NOP or DES
Notes :
1. Shown with nominal value of t_DQSS.
2. t_WR/A starts at the first rising edge of CLK after the last valid edge of WDQS.
3. t_RP starts after t_WR/A has been expired.
4. When issuing a WR/A command please consider that the t_RAS requirement also must be met at the beginning of t_RP.
5. t_WR/A ≥ t_WR.
6. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
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Publication Release Date: Apr, 22, 2011
Revision A01-002