W641GG2JB Datasheet, PDF (62/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.15.2 Bursts with Gaps
6.15.2.1 Consecutive Write Bursts with Gaps
0
1
2
3
CLK#
CLK
Com.
WR
N/D
N/D
WR
4
5
6
7
8
9
10
N/D
DES
DES
DES
DES
DES
DES
Addr.
B/Cx
B/Cy
WDQS
DQ
WL = 3
Dx0 Dx1 Dx2 Dx3
Dy0 Dy1 Dy2 Dy3
WDQS
WL = 4
DQ
Dx0 Dx1 Dx2 Dx3
Dy0 Dy1 Dy2 Dy3
Com. : Command
Addr. : Address B / C
WL : Write Latency
DES : Deselect
N/D : NOP or DES
WR : WRITE
B / Cx: Bank / Column address
B / Cy: Bank / Column address
Dx# : Data to B / Cx
Dy# : Data to B / Cy
Notes :
1. Shown with nominal value of t_DQSS.
2. The second WR command may be either for the same bank or another bank.
3. WDQS can only transition when data is applied at the chip input and during pre- and postambles.
Don’t care
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Publication Release Date: Apr, 22, 2011
Revision A01-002