W641GG2JB Datasheet, PDF (11/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
4. PIN DESCRIPTION
4.1 Signal Description
Ball
Type
Detailed Function
CLK, CLK#
Input
Clock:CLK and CLK# are differential clock inputs. Command and address inputs are latched on the rising edge
of CLK. All latencies are referenced to CLK. CLK and CLK# are not internally terminated.
CKE
Input
Clock Enable:CKE High activates and CKE Low deactivates internal clock, device input buffers and output
drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operations (all banks idle), or Active
Power-Down (row active in any bank). CKE is synchronous for Power-Down entry and exit and for Self Refresh
entry. CKE must be maintained High throughout READ, WRITE and bus snoop bursts.
Input buffers excluding CLK, CLK# and CKE are disabled during Power-Down. Input buffers excluding CKE are
disabled during Self Refresh.
The value of CKE latched at power-up with RES going High determines the termination value of the address and
command inputs.
CS0#,CS1#
Input
Chip Select:Chip Select: CS# Low enables, and CS# High disables the command decoder. All commands
except DTERDIS are masked when CS# is registered High, but internal command execution continues. CS#
provides for individual device selection on memory channels with multiple memory devices. CS# is considered
part of the command code.
In 1-CS mode only CS0# is available.
In 2-CS mode both CS0# and CS1# are available, and CS0# is exclusively used for Mode Register or Extended
Mode Register programming and self refresh entry.
RAS#,CAS#,
WE#
Input
Command Inputs:Command inputs: RAS#, CAS# and WE# (along with CS0# or CS1#) define the command
to be entered.
BA0-BA2
Input
Bank Address Inputs:BA0-BA2 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command
is being applied. BA0-BA2 also determine which Mode Register or Extended Mode Register is accessed with a
MODE REGISTER SET command.
A0-A11 (A12) Input
Address Inputs:Address inputs: provide the row address for ACTIVE commands and the column address
and auto precharge function (A8) for READ and WRITE commands, to select one location out of the memory
array in the respective bank. A8 sampled during a PRECHARGE command determines whether the
PRECHARGE applies to one bank (A8 Low, bank selected by BA0- BA2) or all banks (A8 High). The address
inputs also provide the op-code during an MODE REGISTER SET command.
A12 is the MSB row address in 1-CS mode.
DQ0-DQ31
DM0-DM3
RDQS0-
RDQS3
WDQS0-
WDQS3
ZQ
I/O
Data Inputs/Outputs:Data Input/Output: 32 bit data bus
Input
Output
Input Data Masks:Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled High along with that input data during a WRITE access. DM is sampled on the rising and falling
edges of WDQS. DM0 is associated with DQ0-DQ7, DM1 with DQ8-DQ15, DM2 with DQ16-DQ23 and DM3 with
DQ24-DQ31.
Read Data Strobes: Output with read data. RDQS is edge-aligned with read data.
RDQS0 is associated with DQ0-DQ7, RDQS1 with DQ8-DQ15, RDQS2 with DQ16-DQ23 and RDQS3 with
DQ24-DQ31.
Input
Write Data Strobes:WRITE Data strobe: Input with write data. WDQS is center-aligned to the input data.
WDQS0 is associated with DQ0-DQ7, WDQS1 with DQ8-DQ15, WDQS2 with DQ16-DQ23 and WDQS3 with
DQ24-DQ31.
Reference ODT Impedance Reference: The ZQ ball is used to control the ODT impedance.
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Publication Release Date: Apr, 22, 2011
Revision A01-002