W641GG2JB Datasheet, PDF (12/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

RES
MF
SEN
V_REF
V_DDQ
V_SSQ
V_DD
V_SS
RFU
RAR
W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
Input
Reset pin:The RES pin is a Vddq CMOS input. RES is not internally terminated. When RES is at LOW state
the chip goes into full reset. The chip stays in full reset until RES goes to HIGH state.
The Low to High transition of the RES signal is used to latch the CKE value to set the
value of the termination resistors of the address and command inputs. After exiting the
full reset a complete initialization is required since the full reset sets the internal settings
to default, including mode register bits.
Input
Mirror function :MF is a VDDQ CMOS input. This pin must be hardwired on board either to a power or to a
ground plane. With MF set to HIGH, the command and address pins are reassigned in order to allow for an
easier routing on board for a back to back memory arrangement.
Input ^{Scan Enable:SEN is a VDDQ CMOS input. Must be tied to Ground when not in use.}
Supply Reference voltage for command, address and data inputs.
Supply ^{Isolated power for the input and output buffers .}
Supply ^{Isolated ground for the input and output buffers.}
Supply ^{Power Supply}
Supply Ground
Reserved
Reserved for alternate rank (see ballouts)
4.2 Addressing
Number of ranks
Row Address
Column addresses
Bank address
Auto precharge
Page size
Refresh
2-CS Mode (CS0#,CS1#)
2
A0-A11
A2-A7,A9
BA0-BA2
A8/AP
2 KB
8K/32 mS
1-CS Mode (CS0#)
1
A0-A12
A2-A7,A9
BA0-BA2
A8/AP
2 KB
8K/32 mS
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Publication Release Date: Apr, 22, 2011
Revision A01-002