W641GG2JB Datasheet, PDF (50/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.7.8 Output Driver Impedance
Bits A0 and A1 define the driver strength. The Auto Calibration setting enables the Auto-Calibration functionality for the Pulldown,
Pullup and Termination over process, temperature and voltage changes. The 35Ω, 40Ω and 4Ω5 options enable factory settings for
the Pulldown, Pullup driver strength and termination.
With any of those options enabled, driver strength and termination are expected to change with process, voltage and temperature.
AC timings are only guaranteed with Auto Calibration.
6.7.9 Data Termination
Bits A2 and A3 define the data termination value for the on-die termination (ODT) for the DQ pins in combination with
the driver strength setting. The termination can be set to a value of ZQ/4 or ZQ/2; it may also be turned off.
6.7.10 Address command termination
Bits A8 and A9 define the address/command termination. The termination can be set to a value of ZQ/4, ZQ/2 or ZQ. The setting
overwrites the value defined upon power-up initialization.
6.8 Extended Mode Register 2 Set Command (EMRS2)
The Extended Mode Register 2 is used to control OCD/ODT impedance offsets. It can be programmed by performing a normal
Mode Register Set operation and setting the BA1 bit to HIGH and BA0, BA2 bits to LOW. The Extended Mode Register 2 must be
loaded when all banks are idle and no burst are in progress. The controller must wait the specified time tMRD before initiating any
subsequent operation. The timing of the EMRS2 command operation is equivalent to the timing of the MRS command operation.
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Publication Release Date: Apr, 22, 2011
Revision A01-002