W641GG2JB Datasheet, PDF (72/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.16.2 Read - Basic Sequence
6.16.2.1 Read Burst
0
1
2
3
6
7
8
9
10
11
CLK#
CLK
Com.
RD
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
Addr.
B/C
RDQS
DQ
CAS latency = 5
D0 D1 D2 D3
CAS latency = 6
RDQS
DQ
D0 D1 D2 D3
B / C: Bank / Column address
Dx : Data from B / C
Com. : Command
Addr. : Address B / C
RD : READ
N/D : NOP or Deselect
Don‘t care
DQs : Terminations off
RDQS : Not driven
Notes :
1. Shown with nominal t_AC and t_DQSQ.
2. RDQS will start driving high 1/2 cycle prior to the first falling edge and stop 1/2 cycle after the last rising edge of RDQS.
3. The DQ terminations are switched off 1 cycle before the first Read Data and on again 1 cycle after the last Read data.
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Publication Release Date: Apr, 22, 2011
Revision A01-002