W641GG2JB Datasheet, PDF (54/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.11 Bank / Row Activation (ACT)
Before a READ or WRITE command can be issued to a bank, a row in that bank must be opened. This is accomplished via the ACT
command, which selects both the bank and the row to be activated.After opening a row by issuing an ACT command, a READ
command may be issued after t_RCDRD to that row or a WRITE command after t_RCDWR.
A subsequent ACT command to a different row in the same bank can only be issued after the previous active row has been closed
(precharged). The minimum time interval between successive ACT commands to the same bank is defined by t_RC.
A subsequent ACT command to another bank can be issued while the first bank is being accessed, which results in a reduction of
total row-access overhead. The minimum time interval between successive ACT commands to ACT commands to banks in the
same rank is defined by t_RRD, and ^{to banks in different ranks by t}RRD_RR ^{(see Figure:}Bank Activation Timing on different rank in
2-CS mode^{).There is a minimum time t}RAS ^{between opening and closing a row.}
For the 1-CS Mode (1Gb) an additional address bit is available (A12). Internally this additional address bit is converted into a
selection signal for one or the other internal rank representing the first or the second half of the 512 Mb. Subsequent column
accesses to the activated bank are steered to the internal rank as selected by A12 during activation of the bank.
6.11.1 Activating a specific row
CLK#
CLK
CKE
CS#
RAS#
CAS#
WE#
A0-A11
RA
BA0-BA2
BA
RA : Row address
BA : Bank Address
Don‘t care
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Publication Release Date: Apr, 22, 2011
Revision A01-002