W641GG2JB Datasheet, PDF (91/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.22 Power-Down
The GDDR3 requires CKE to be active at all times an access is in progress: From the issuing of a READ or WRITE command until
completion of the burst. For READs, a burst completion is defined after the rising edge of the Read Postamble. For Writes, a burst
completion is defined one clock after the rising edge of the Write Postamble.
For Read with Autoprecharge and Write with Autoprecharge, the internal Autoprecharge must be completed before entering Power-
Down.
Power-Down is entered when CKE is registered LOW. (No access can be in progress. "Access" means as well READ or WRITE to a
second memory sharing the data bus in a dual rank system.) If Power-Down occurs when all banks are idle, this mode is referred to
as Precharge Power-Down; if Power- Down occurs when there is a row active in any bank, this mode is referred to as Active Power-
Down. Entering power- down deactivates the input and output buffers, excluding CLK, CLK# and CKE. For maximum power saving,
the user has the option of disabling the DLL prior to entering power- down. In that case the DLL must be enabled and reset after
exiting power-down, and 1000 cycles must occur before a READ command can be issued.
In Power-Down mode, CKE low and a stable clock signal must be maintained at the inputs of the GDDR3 Graphics RAM, all the
other input signals are ―Don‘t Care‖. Power down duration is limited by the refresh requirements of the device.
The Power-Down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESEL command). A valid
executable command may be applied t_XPN later.
6.22.1 Power Down Command
- 91 -
Publication Release Date: Apr, 22, 2011
Revision A01-002