W641GG2JB Datasheet, PDF (42/109 Pages) Winbond – 1-Gbit GDDR3 Graphics SDRAM

W641GG2JB
1-Gbit GDDR3 Graphics SDRAM
6.6 Mode Register Set Command (MRS)
The Mode Register stores the data for controlling the operation modes of the memory. It programs CAS latency, test mode, DLL
Reset, the value of the Write Latency and the Burst length. The Mode Register must be written after power up to operate the
SGRAM. During a Mode Register Set command the address inputs are sampled and stored in the Mode Register. The mode
Register content can only be set or changed when the chip is in idle state. For non-READ commands following a Mode Register Set
a delay of tMRD must be met.
To apply an MRS command, CS0 has to be used.
6.6.1 Mode Register Set Command
CLK#
CLK
CKE
CS#
(High)
RAS#
CAS#
WE#
A0-A11
COD
BA0
0
BA1, BA2
0
COD: Code to be loaded
into the register.
= Don't Care
6.6.2 Mode Registers
Three Mode Registers MRS, EMRS1 and EMRS2 define the specific mode of operation. All Mode Registers are initialized upon
power-up as indicated below.
All functions controlled by Mode Register EMRS3 and some high-speed options in the other registers as outlined below shall be
deactivated or deleted such that programming of the respective register bits has no effect.
6.6.2.1 Mode Register (MRS)
The Mode Register controls operating modes such as Burst Length, Burst Type, CAS latency, Write Latency, DLL Reset and Test
Mode as shown in Figure . The register is programmed via the MODE REGISTER SET command with BA0=0, BA1=0 and BA2=0.
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Publication Release Date: Apr, 22, 2011
Revision A01-002