LM3S1651 Datasheet, PDF (950/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Signal Tables
Table 21-8. Signals by Signal Name (continued)
Pin Name
GNDA
Pin Number Pin Mux / Pin
Assignment
A5
fixed
Pin Type
-
HIB
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
I2S0RXMCLK
I2S0RXSCK
I2S0RXSD
I2S0RXWS
I2S0TXMCLK
I2S0TXSCK
I2S0TXSD
I2S0TXWS
IDX0
IDX1
LDO
M12
fixed
O
A11
PB2 (1)
I/O
E11
PB3 (1)
I/O
F3
PJ0 (11)
I/O
K1
PG0 (3)
L3
PA0 (8)
L6
PA6 (1)
K2
PG1 (3)
I/O
M3
PA1 (8)
M6
PA7 (1)
B6
PJ1 (11)
J2
PG3 (9)
I/O
L4
PA3 (9)
C6
PD5 (8)
G1
PD0 (8)
I/O
M7
PG5 (9)
J1
PG2 (9)
I/O
M4
PA2 (9)
B5
PD4 (8)
G2
PD1 (8)
I/O
L7
PG6 (9)
M8
PF6 (9)
I/O
H12
PF1 (8)
L5
PA4 (9)
I/O
A7
PB6 (9)
A3
PD6 (8)
B3
PE5 (9)
I/O
M9
PF0 (8)
B2
PE4 (9)
I/O
M5
PA5 (9)
A2
PD7 (8)
G1
PD0 (3)
I
M7
PG5 (4)
A11
PB2 (2)
A7
PB6 (5)
A6
PB4 (6)
A2
PD7 (1)
J1
PG2 (8)
I
H12
PF1 (2)
D11
PH2 (1)
E3
fixed
-
Buffer Type^a Description
Power
OD
OD
OD
OD
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
An output that indicates the processor is in
Hibernate mode.
I²C module 0 clock.
I²C module 0 data.
I²C module 1 clock.
OD
I²C module 1 data.
TTL
I²S module 0 receive master clock.
TTL
I²S module 0 receive clock.
TTL
I²S module 0 receive data.
TTL
I²S module 0 receive word select.
TTL
I²S module 0 transmit master clock.
TTL
I²S module 0 transmit clock.
TTL
I²S module 0 transmit data.
TTL
I²S module 0 transmit word select.
TTL
QEI module 0 index.
TTL
QEI module 1 index.
Power
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. The LDO pin must also be
connected to the VDDC pins at the board level in
addition to the decoupling capacitor(s).
950
January 21, 2012
Texas Instruments-Production Data