LM3S1651 Datasheet, PDF (777/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1651 Microcontroller
Register 7: I²S Receive FIFO Data (I2SRXFIFO), offset 0x800
Important: This register is read-sensitive. See the register description for details.
This register is the 32-bit serial audio receive data register. In Stereo mode, the data is read left,
right, left, right, and so on. The LRS bit in the I²S Receive FIFO Configuration (I2SRXFIFOCFG)
register can be read to verify the next position expected. In Compact 16-bit mode, bits [31:16] contain
the right sample, and bits [15:0] contain the left sample. In Compact 8-bit mode, bits [15:8] contain
the right sample, and bits [7:0] contain the left sample. In Mono mode, each 32-bit entry is a single
sample. If the FIFO is empty, a read of this register returns a value of 0x0000.0000 and generates
a receive FIFO read error.
I2S Receive FIFO Data (I2SRXFIFO)
Base 0x4005.4000
Offset 0x800
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RXFIFO
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RXFIFO
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
RXFIFO
Type
Reset Description
RO 0x0000.0000 RX Data
Serial audio sample data received.
The read of an empty FIFO returns a value of 0x0.
January 21, 2012
777
Texas Instruments-Production Data