LM3S1651 Datasheet, PDF (10/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 3-1.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 8-5.
Figure 8-6.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 10-5.
Figure 11-1.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 12-6.
Stellaris LM3S1651 Microcontroller High-Level Block Diagram ............................... 40
CPU Block Diagram ............................................................................................. 61
TPIU Block Diagram ............................................................................................ 62
Cortex-M3 Register Set ........................................................................................ 64
Bit-Band Mapping ................................................................................................ 84
Data Storage ....................................................................................................... 85
Vector Table ........................................................................................................ 91
Exception Stack Frame ........................................................................................ 93
SRD Use Example ............................................................................................. 108
JTAG Module Block Diagram .............................................................................. 169
Test Access Port State Machine ......................................................................... 172
IDCODE Register Format ................................................................................... 178
BYPASS Register Format ................................................................................... 178
Boundary Scan Register Format ......................................................................... 179
Basic RST Configuration .................................................................................... 183
External Circuitry to Extend Power-On Reset ....................................................... 183
Reset Circuit Controlled by Switch ...................................................................... 184
Power Architecture ............................................................................................ 187
Main Clock Tree ................................................................................................ 190
Hibernation Module Block Diagram ..................................................................... 284
Using a Crystal as the Hibernation Clock Source ................................................. 287
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 287
Internal Memory Block Diagram .......................................................................... 310
μDMA Block Diagram ......................................................................................... 348
Example of Ping-Pong μDMA Transaction ........................................................... 354
Memory Scatter-Gather, Setup and Configuration ................................................ 356
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 357
Peripheral Scatter-Gather, Setup and Configuration ............................................. 359
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 360
Digital I/O Pads ................................................................................................. 410
Analog/Digital I/O Pads ...................................................................................... 411
GPIODATA Write Example ................................................................................. 412
GPIODATA Read Example ................................................................................. 412
GPTM Module Block Diagram ............................................................................ 462
Timer Daisy Chain ............................................................................................. 468
Input Edge-Count Mode Example ....................................................................... 470
16-Bit Input Edge-Time Mode Example ............................................................... 471
16-Bit PWM Mode Example ................................................................................ 472
WDT Module Block Diagram .............................................................................. 509
Implementation of Two ADC Blocks .................................................................... 534
ADC Module Block Diagram ............................................................................... 535
ADC Sample Phases ......................................................................................... 539
Doubling the ADC Sample Rate .......................................................................... 540
Skewed Sampling .............................................................................................. 540
Sample Averaging Example ............................................................................... 541
10
January 21, 2012
Texas Instruments-Production Data