LM3S1651 Datasheet, PDF (484/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

General-Purpose Timers
Bit/Field
11:10
9
8
7
6
5
Name
TBEVENT
TBSTALL
TBEN
reserved
TAPWML
TAOTE
Type
R/W
R/W
R/W
RO
R/W
R/W
Reset
0x0
Description
GPTM Timer B Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
0
GPTM Timer B Stall Enable
The TBSTALL values are defined as follows:
Value Description
0 Timer B continues counting while the processor is halted by the
debugger.
1 Timer B freezes counting while the processor is halted by the
debugger.
If the processor is executing normally, the TBSTALL bit is ignored.
0
GPTM Timer B Enable
The TBEN values are defined as follows:
Value Description
0 Timer B is disabled.
1 Timer B is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
GPTM Timer A PWM Output Level
The TAPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
0
GPTM Timer A Output Trigger Enable
The TAOTE values are defined as follows:
Value Description
0 The output Timer A ADC trigger is disabled.
1 The output Timer A ADC trigger is enabled.
In addition, the ADC must be enabled and the timer selected as a trigger
source with the EMn bit in the ADCEMUX register (see page 566).
484
January 21, 2012
Texas Instruments-Production Data