LM3S1651 Datasheet, PDF (25/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1651 Microcontroller
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 749
I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 750
I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 752
I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 753
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 754
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 755
I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 756
Inter-Integrated Circuit Sound (I²S) Interface ............................................................................ 757
Register 1: I²S Transmit FIFO Data (I2STXFIFO), offset 0x000 .......................................................... 770
Register 2: I²S Transmit FIFO Configuration (I2STXFIFOCFG), offset 0x004 ...................................... 771
Register 3: I²S Transmit Module Configuration (I2STXCFG), offset 0x008 .......................................... 772
Register 4: I²S Transmit FIFO Limit (I2STXLIMIT), offset 0x00C ........................................................ 774
Register 5: I²S Transmit Interrupt Status and Mask (I2STXISM), offset 0x010 ..................................... 775
Register 6: I²S Transmit FIFO Level (I2STXLEV), offset 0x018 .......................................................... 776
Register 7: I²S Receive FIFO Data (I2SRXFIFO), offset 0x800 .......................................................... 777
Register 8: I²S Receive FIFO Configuration (I2SRXFIFOCFG), offset 0x804 ...................................... 778
Register 9: I²S Receive Module Configuration (I2SRXCFG), offset 0x808 ........................................... 779
Register 10: I²S Receive FIFO Limit (I2SRXLIMIT), offset 0x80C ......................................................... 782
Register 11: I²S Receive Interrupt Status and Mask (I2SRXISM), offset 0x810 ..................................... 783
Register 12: I²S Receive FIFO Level (I2SRXLEV), offset 0x818 ........................................................... 784
Register 13: I²S Module Configuration (I2SCFG), offset 0xC00 ............................................................ 785
Register 14: I²S Interrupt Mask (I2SIM), offset 0xC10 ......................................................................... 787
Register 15: I²S Raw Interrupt Status (I2SRIS), offset 0xC14 ............................................................... 789
Register 16: I²S Masked Interrupt Status (I2SMIS), offset 0xC18 ......................................................... 791
Register 17: I²S Interrupt Clear (I2SIC), offset 0xC1C ......................................................................... 793
Analog Comparators ................................................................................................................... 794
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 800
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 801
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 802
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 803
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 804
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x040 ..................................................... 804
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x024 ..................................................... 805
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x044 ..................................................... 805
Pulse Width Modulator (PWM) .................................................................................................... 807
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 822
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 823
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 824
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 826
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 828
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 830
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 832
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 834
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 836
Register 10: PWM Fault Condition Value (PWMFAULTVAL), offset 0x024 ............................................ 838
Register 11: PWM Enable Update (PWMENUPD), offset 0x028 ........................................................... 840
January 21, 2012
25
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