LM3S1651 Datasheet, PDF (473/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1651 Microcontroller
10.3.4
10.4
10.4.1
No other special steps are needed to enable Timers for μDMA operation. Refer to “Micro Direct
Memory Access (μDMA)” on page 347 for more details about programming the μDMA controller.
Accessing Concatenated Register Values
The GPTM is placed into concatenated mode by writing a 0x0 or a 0x1 to the GPTMCFG bit field in
the GPTM Configuration (GPTMCFG) register. In both configurations, certain registers are
concatenated to form pseudo 32-bit registers. These registers include:
■ GPTM Timer A Interval Load (GPTMTAILR) register [15:0], see page 496
■ GPTM Timer B Interval Load (GPTMTBILR) register [15:0], see page 497
■ GPTM Timer A (GPTMTAR) register [15:0], see page 504
■ GPTM Timer B (GPTMTBR) register [15:0], see page 505
■ GPTM Timer A Value (GPTMTAV) register [15:0], see page 506
■ GPTM Timer B Value (GPTMTBV) register [15:0], see page 507
■ GPTM Timer A Match (GPTMTAMATCHR) register [15:0], see page 498
■ GPTM Timer B Match (GPTMTBMATCHR) register [15:0], see page 499
In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access
to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is:
GPTMTBILR[15:0]:GPTMTAILR[15:0]
Likewise, a 32-bit read access to GPTMTAR returns the value:
GPTMTBR[15:0]:GPTMTAR[15:0]
A 32-bit read access to GPTMTAV returns the value:
GPTMTBV[15:0]:GPTMTAV[15:0]
Initialization and Configuration
To use a GPTM, the appropriate TIMERn bit must be set in the RCGC1 register (see page 261). If
using any CCP pins, the clock to the appropriate GPIO module must be enabled via the RCGC1
register (see page 261). To find out which GPIO port to enable, refer to Table 21-4 on page 925.
Configure the PMCn fields in the GPIOPCTL register to assign the CCP signals to the appropriate
pins (see page 447 and Table 21-5 on page 932).
This section shows module initialization and configuration examples for each of the supported timer
modes.
One-Shot/Periodic Timer Mode
The GPTM is configured for One-Shot and Periodic modes by the following sequence:
1. Ensure the timer is disabled (the TnEN bit in the GPTMCTL register is cleared) before making
any changes.
2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0000.0000.
January 21, 2012
473
Texas Instruments-Production Data