LM3S1651 Datasheet, PDF (723/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1651 Microcontroller
Figure 15-5. R/S Bit in First Byte
MSB
LSB
R/S
Slave address
15.3.1.3
Data Validity
The data on the SDA line must be stable during the high period of the clock, and the data line can
only change when SCL is Low (see Figure 15-6).
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus
SDA
SCL
Data line Change
stable of data
allowed
15.3.1.4
Acknowledge
All bus transactions have a required acknowledge clock cycle that is generated by the master. During
the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line.
To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock
cycle. The data transmitted out by the receiver during the acknowledge cycle must comply with the
data validity requirements described in “Data Validity” on page 723.
When a slave receiver does not acknowledge the slave address, SDA must be left High by the slave
so that the master can generate a STOP condition and abort the current transfer. If the master
device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer
made by the slave. Because the master controls the number of bytes in the transfer, it signals the
end of data to the slave transmitter by not generating an acknowledge on the last data byte. The
slave transmitter must then release SDA to allow the master to generate the STOP or a repeated
START condition.
15.3.1.5
Arbitration
A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate
a START condition within minimum hold time of the START condition. In these situations, an
arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of
the competing master devices to place a '1' (High) on SDA while another master transmits a '0'
(Low) switches off its data output stage and retires until the bus is idle again.
Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if
both masters are trying to address the same device, arbitration continues on to the comparison of
data bits.
15.3.2
Available Speed Modes
The I²C bus can run in either Standard mode (100 kbps) or Fast mode (400 kbps). The selected
mode should match the speed of the other I²C devices on the bus.
January 21, 2012
723
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