LM3S1651 Datasheet, PDF (5/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1651 Microcontroller
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Hibernation Module .............................................................................................. 283
6.1 Block Diagram ............................................................................................................ 284
6.2 Signal Description ....................................................................................................... 284
6.3 Functional Description ................................................................................................. 285
6.3.1 Register Access Timing ............................................................................................... 285
6.3.2 Hibernation Clock Source ............................................................................................ 286
6.3.3 System Implementation ............................................................................................... 287
6.3.4 Battery Management ................................................................................................... 288
6.3.5 Real-Time Clock .......................................................................................................... 288
6.3.6 Battery-Backed Memory .............................................................................................. 289
6.3.7 Power Control Using HIB ............................................................................................. 289
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 289
6.3.9 Initiating Hibernate ...................................................................................................... 289
6.3.10 Waking from Hibernate ................................................................................................ 289
6.3.11 Interrupts and Status ................................................................................................... 290
6.4 Initialization and Configuration ..................................................................................... 290
6.4.1 Initialization ................................................................................................................. 290
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 291
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 291
6.4.4 External Wake-Up from Hibernation .............................................................................. 292
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 292
6.5 Register Map .............................................................................................................. 292
6.6 Register Descriptions .................................................................................................. 293
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7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Internal Memory ................................................................................................... 310
Block Diagram ............................................................................................................ 310
Functional Description ................................................................................................. 310
SRAM ........................................................................................................................ 311
ROM .......................................................................................................................... 311
Flash Memory ............................................................................................................. 313
Register Map .............................................................................................................. 318
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 319
Memory Register Descriptions (System Control Offset) .................................................. 331
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Micro Direct Memory Access (μDMA) ................................................................ 347
8.1 Block Diagram ............................................................................................................ 348
8.2 Functional Description ................................................................................................. 348
8.2.1 Channel Assignments .................................................................................................. 349
8.2.2 Priority ........................................................................................................................ 350
8.2.3 Arbitration Size ............................................................................................................ 350
8.2.4 Request Types ............................................................................................................ 350
8.2.5 Channel Configuration ................................................................................................. 351
8.2.6 Transfer Modes ........................................................................................................... 353
8.2.7 Transfer Size and Increment ........................................................................................ 361
8.2.8 Peripheral Interface ..................................................................................................... 361
8.2.9 Software Request ........................................................................................................ 361
8.2.10 Interrupts and Errors .................................................................................................... 362
8.3 Initialization and Configuration ..................................................................................... 362
8.3.1 Module Initialization ..................................................................................................... 362
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 362
January 21, 2012
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