LM3S1651 Datasheet, PDF (20/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Table of Contents
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 333
Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 334
Boot Configuration (BOOTCFG), offset 0x1D0 ................................................................. 335
User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 337
User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 338
User Register 2 (USER_REG2), offset 0x1E8 .................................................................. 339
User Register 3 (USER_REG3), offset 0x1EC ................................................................. 340
Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 341
Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 342
Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 343
Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 344
Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 345
Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 346
Micro Direct Memory Access (μDMA) ........................................................................................ 347
Register 1: DMA Channel Source Address End Pointer (DMASRCENDP), offset 0x000 ...................... 370
Register 2: DMA Channel Destination Address End Pointer (DMADSTENDP), offset 0x004 ................ 371
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008 .................................................. 372
Register 4: DMA Status (DMASTAT), offset 0x000 ............................................................................ 377
Register 5: DMA Configuration (DMACFG), offset 0x004 ................................................................... 379
Register 6: DMA Channel Control Base Pointer (DMACTLBASE), offset 0x008 .................................. 380
Register 7: DMA Alternate Channel Control Base Pointer (DMAALTBASE), offset 0x00C .................... 381
Register 8: DMA Channel Wait-on-Request Status (DMAWAITSTAT), offset 0x010 ............................. 382
Register 9: DMA Channel Software Request (DMASWREQ), offset 0x014 ......................................... 383
Register 10: DMA Channel Useburst Set (DMAUSEBURSTSET), offset 0x018 .................................... 384
Register 11: DMA Channel Useburst Clear (DMAUSEBURSTCLR), offset 0x01C ................................. 385
Register 12: DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 386
Register 13: DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 387
Register 14: DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 388
Register 15: DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 389
Register 16: DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 390
Register 17: DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 391
Register 18: DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 392
Register 19: DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 393
Register 20: DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 394
Register 21: DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 395
Register 22: DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 396
Register 23: DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 397
Register 24: DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 398
Register 25: DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 399
Register 26: DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 400
Register 27: DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 401
Register 28: DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 402
Register 29: DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 403
Register 30: DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 404
General-Purpose Input/Outputs (GPIOs) ................................................................................... 405
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 419
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 420
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 421
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January 21, 2012
Texas Instruments-Production Data