LM3S1651 Datasheet, PDF (22/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Table of Contents
Register 17:
Register 18:
Register 19:
Register 20:
GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 504
GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 505
GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 506
GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 507
Watchdog Timers ......................................................................................................................... 508
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 512
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 513
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 514
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 516
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 517
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 518
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 519
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 520
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 521
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 522
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 523
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 524
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 525
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 526
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 527
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 528
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 529
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 530
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 531
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 532
Analog-to-Digital Converter (ADC) ............................................................................................. 533
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 556
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 557
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 559
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 561
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 564
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 566
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 571
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 572
Register 9: ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 574
Register 10: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 576
Register 11: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 578
Register 12: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 579
Register 13: ADC Control (ADCCTL), offset 0x038 ............................................................................. 581
Register 14: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 582
Register 15: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 584
Register 16: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 587
Register 17: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 587
Register 18: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 587
Register 19: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 587
Register 20: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 588
Register 21: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 588
Register 22: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 588
22
January 21, 2012
Texas Instruments-Production Data