LM3S1651 Datasheet, PDF (772/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Inter-Integrated Circuit Sound (I²S) Interface
Register 3: I²S Transmit Module Configuration (I2STXCFG), offset 0x008
This register controls the configuration of the Transmit module.
I2S Transmit Module Configuration (I2STXCFG)
Base 0x4005.4000
Offset 0x008
Type R/W, reset 0x1400.7DF0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
JST
DLY
SCP
LRP
WM
FMT
MSL
reserved
Type RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
Reset
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SSZ
SDSZ
reserved
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Reset
0
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
Bit/Field
31:30
29
Name
reserved
JST
Type
RO
R/W
Reset
0x0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Justification of Output Data
Value Description
0 The data is Left-Justified.
1 The data is Right-Justified.
28
DLY
R/W
1
Data Delay
Value Description
0 Data is latched on the next latching edge of I2S0TXSCK as
defined by the SCP bit. This bit should be clear in Left-Justified
or Right-Justified mode.
1 A one-I2S0TXSCK delay from the edge of I2S0TXWS is inserted
before data is latched. This bit should be set in I²S mode.
27
SCP
R/W
0
SCLK Polarity
Value Description
0 Data and the I2S0TXWS signal (when the MSL bit is set) are
launched on the falling edge of I2S0TXSCK.
1 Data and the I2S0TXWS signal (when the MSL bit is set) are
launched on the rising edge of I2S0TXSCK.
26
LRP
R/W
1
Left/Right Clock Polarity
Value Description
0 I2S0TXWS is high during the transmission of the left channel
data.
1 I2S0TXWS is high during the transmission of the right channel
data.
772
January 21, 2012
Texas Instruments-Production Data