LM3S1651 Datasheet, PDF (689/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1651 Microcontroller
14.4
single and burst µDMA transfer requests are handled automatically by the μDMA controller depending
how the µDMA channel is configured. To enable µDMA operation for the receive channel, the
RXDMAE bit of the DMA Control (SSIDMACTL) register should be set. To enable µDMA operation
for the transmit channel, the TXDMAE bit of SSIDMACTL should be set. If µDMA is enabled, then
the μDMA controller triggers an interrupt when a transfer is complete. The interrupt occurs on the
SSI interrupt vector. Therefore, if interrupts are used for SSI operation and µDMA is enabled, the
SSI interrupt handler must be designed to handle the μDMA completion interrupt.
See “Micro Direct Memory Access (μDMA)” on page 347 for more details about programming the
μDMA controller.
Initialization and Configuration
To enable and initialize the SSI, the following steps are necessary:
1. Enable the SSI module by setting the SSI bit in the RCGC1 register (see page 261).
2. Enable the clock to the appropriate GPIO module via the RCGC2 register (see page 270). To
find out which GPIO port to enable, refer to Table 21-5 on page 932.
3. Set the GPIO AFSEL bits for the appropriate pins (see page 429). To determine which GPIOs to
configure, see Table 21-4 on page 925.
4. Configure the PMCn fields in the GPIOPCTL register to assign the SSI signals to the appropriate
pins. See page 447 and Table 21-5 on page 932.
For each of the frame formats, the SSI is configured using the following steps:
1. Ensure that the SSE bit in the SSICR1 register is clear before making any configuration changes.
2. Select whether the SSI is a master or slave:
a. For master operations, set the SSICR1 register to 0x0000.0000.
b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
3. Configure the clock prescale divisor by writing the SSICPSR register.
4. Write the SSICR0 register with the following configuration:
■ Serial clock rate (SCR)
■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
■ The data size (DSS)
5. Optionally, configure the μDMA channel (see “Micro Direct Memory Access (μDMA)” on page 347)
and enable the DMA option(s) in the SSIDMACTL register.
6. Enable the SSI by setting the SSE bit in the SSICR1 register.
As an example, assume the SSI must be configured to operate with the following parameters:
January 21, 2012
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