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LM3S1651 Datasheet, PDF (90/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark
The Cortex-M3 Processor
2.5.3
Table 2-9. Interrupts (continued)
Vector Number
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55-58
59
60-61
62
63
64
65
66
67
68
69
70
Interrupt Number (Bit
in Interrupt Registers)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39-42
43
44-45
46
47
48
49
50
51
52
53
54
Vector Address or
Offset
0x0000.0080
0x0000.0084
0x0000.0088
0x0000.008C
0x0000.0090
0x0000.0094
0x0000.0098
0x0000.009C
0x0000.00A0
0x0000.00A4
0x0000.00A8
-
0x0000.00B0
0x0000.00B4
0x0000.00B8
0x0000.00BC
0x0000.00C0
0x0000.00C4
0x0000.00C8
0x0000.00CC
0x0000.00D0
0x0000.00D4
0x0000.00D8
-
0x0000.00EC
-
0x0000.00F8
0x0000.00FC
0x0000.0100
0x0000.0104
0x0000.0108
0x0000.010C
0x0000.0110
-
0x0000.0118
Description
ADC0 Sequence 2
ADC0 Sequence 3
Watchdog Timers 0 and 1
Timer 0A
Timer 0B
Timer 1A
Timer 1B
Timer 2A
Timer 2B
Analog Comparator 0
Analog Comparator 1
Reserved
System Control
Flash Memory Control
GPIO Port F
GPIO Port G
GPIO Port H
UART2
SSI1
Timer 3A
Timer 3B
I2C1
QEI1
Reserved
Hibernation Module
Reserved
µDMA Software
µDMA Error
ADC1 Sequence 0
ADC1 Sequence 1
ADC1 Sequence 2
ADC1 Sequence 3
I2S0
Reserved
GPIO Port J
Exception Handlers
The processor handles exceptions using:
■ Interrupt Service Routines (ISRs). Interrupts (IRQx) are the exceptions handled by ISRs.
90
January 21, 2012
Texas Instruments-Production Data