LM3S1651 Datasheet, PDF (32/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Revision History
Table 1. Revision History (continued)
Date
September 2010
Revision Description
7794
■ Reorganized ARM Cortex-M3 Processor Core, Memory Map and Interrupts chapters, creating two
new chapters, The Cortex-M3 Processor and Cortex-M3 Peripherals. Much additional content was
added, including all the Cortex-M3 registers.
■ Changed register names to be consistent with StellarisWare^® names: the Cortex-M3 Interrupt
Control and Status (ICSR) register to the Interrupt Control and State (INTCTRL) register, and
the Cortex-M3 Interrupt Set Enable (SETNA) register to the Interrupt 0-31 Set Enable (EN0)
register.
■ In the System Control chapter:
– Corrected Reset Sources table (see Table 5-3 on page 181).
– Added section "Special Considerations for Reset."
■ In the Hibernation Module chapter, added section "Special Considerations When Using a
4.194304-MHz Crystal".
■ In the Internal Memory chapter:
– Added clarification of instruction execution during Flash operations.
– Deleted ROM Version (RMVER) register as it is not used.
■ Modified Figure 9-1 on page 410 and Figure 9-2 on page 411 to clarify operation of the GPIO inputs
when used as an alternate function.
■ Corrected GPIOAMSEL bit field in GPIO Analog Mode Select (GPIOAMSEL) register to be eight-bits
wide, bits[7:0].
■ In General-Purpose Timers chapter, clarified operation of the 32-bit RTC mode.
■ In Operating Characteristics chapter, corrected Thermal resistance (junction to ambient) value to
32.
■ In Electrical Characteristics chapter:
– Added "Input voltage for a GPIO configured as an analog input" value to Table 23-1 on page 971.
– Added I_LKG parameter (GPIO input leakage current) to Table 23-20 on page 981.
– Corrected Nom values for I_{HIB_NORTC} and I_{HIB_RTC} in Table 23-32 on page 988.
– Corrected reset timing in Table 23-5 on page 975.
– Corrected values for t_{WAKE_TO_HIB} in Table 23-18 on page 980.
– Specified Max value for V_REFA in Table 23-22 on page 983.
– Corrected values for t_CLKRF (SSIClk rise/fall time) in Table 23-24 on page 983.
– Added I²C Characteristics table (see Table 23-25 on page 985).
■ Added dimensions for Tray and Tape and Reel shipping mediums.
June 2010
7413 ■ In "Thermal Characteristics" table, corrected thermal resistance value from 34 to 32.
June 2010
7299
■ Removed 4.194304-MHz crystal as a source for the system clock and PLL.
■ Summarized ROM contents descriptions in the "Internal Memory" chapter and removed various
ROM appendices.
■ Clarified DMA channel terminology: changed name of DMA Channel Alternate Select (DMACHALT)
register to DMA Channel Assignment (DMACHASGN) register, changed CHALT bit field to CHASGN,
and changed terminology from primary and alternate channels to primary and secondary channels.
■ In Signal Tables chapter, added table "Connections for Unused Signals."
■ In "Electrical Characteristics" chapter:
– In "Reset Characteristics" table, corrected Supply voltage (VDD) rise time.
– Clarified figure "SDRAM Initialization and Load Mode Register Timing".
32
January 21, 2012
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