LM3S1651 Datasheet, PDF (369/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1651 Microcontroller
Table 8-13. μDMA Register Map (continued)
Offset Name
Type
Reset
Description
0x00C DMAALTBASE
RO
0x010 DMAWAITSTAT
RO
0x014 DMASWREQ
WO
0x018 DMAUSEBURSTSET R/W
0x01C DMAUSEBURSTCLR
WO
0x020 DMAREQMASKSET
R/W
0x024 DMAREQMASKCLR
WO
0x028 DMAENASET
R/W
0x02C DMAENACLR
WO
0x030 DMAALTSET
R/W
0x034 DMAALTCLR
WO
0x038 DMAPRIOSET
R/W
0x03C DMAPRIOCLR
WO
0x04C DMAERRCLR
R/W
0x500 DMACHASGN
R/W
0xFD0 DMAPeriphID4
RO
0xFE0 DMAPeriphID0
RO
0xFE4 DMAPeriphID1
RO
0xFE8 DMAPeriphID2
RO
0xFEC DMAPeriphID3
RO
0xFF0 DMAPCellID0
RO
0xFF4 DMAPCellID1
RO
0xFF8 DMAPCellID2
RO
0xFFC DMAPCellID3
RO
0x0000.0200
0xFFFF.FFC0
-
0x0000.0000
-
0x0000.0000
-
0x0000.0000
-
0x0000.0000
-
0x0000.0000
-
0x0000.0000
0x0000.0000
0x0000.0004
0x0000.0030
0x0000.00B2
0x0000.000B
0x0000.0000
0x0000.000D
0x0000.00F0
0x0000.0005
0x0000.00B1
DMA Alternate Channel Control Base Pointer
DMA Channel Wait-on-Request Status
DMA Channel Software Request
DMA Channel Useburst Set
DMA Channel Useburst Clear
DMA Channel Request Mask Set
DMA Channel Request Mask Clear
DMA Channel Enable Set
DMA Channel Enable Clear
DMA Channel Primary Alternate Set
DMA Channel Primary Alternate Clear
DMA Channel Priority Set
DMA Channel Priority Clear
DMA Bus Error Clear
DMA Channel Assignment
DMA Peripheral Identification 4
DMA Peripheral Identification 0
DMA Peripheral Identification 1
DMA Peripheral Identification 2
DMA Peripheral Identification 3
DMA PrimeCell Identification 0
DMA PrimeCell Identification 1
DMA PrimeCell Identification 2
DMA PrimeCell Identification 3
See
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8.5 μDMA Channel Control Structure
The μDMA Channel Control Structure holds the transfer settings for a μDMA channel. Each channel
has two control structures, which are located in a table in system memory. Refer to “Channel
Configuration” on page 351 for an explanation of the Channel Control Table and the Channel Control
Structure.
The channel control structure is one entry in the channel control table. Each channel has a primary
and alternate structure. The primary control structures are located at offsets 0x0, 0x10, 0x20 and
so on. The alternate control structures are located at offsets 0x200, 0x210, 0x220, and so on.
January 21, 2012
369
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