LM3S1651 Datasheet, PDF (208/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

System Control
Register 6: Reset Cause (RESC), offset 0x05C
This register is set with the reset cause after reset. The bits in this register are sticky and maintain
their state across multiple reset sequences, except when an power-on reset is the cause, in which
case, all bits other than POR in the RESC register are cleared.
Reset Cause (RESC)
Base 0x400F.E000
Offset 0x05C
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
MOSCFAIL
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
WDT1
SW
WDT0 BOR
POR
EXT
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
Bit/Field
31:17
16
Name
reserved
MOSCFAIL
Type
RO
R/W
Reset
0x000
-
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
MOSC Failure Reset
Value Description
1 When read, this bit indicates that the MOSC circuit was enabled
for clock validation and failed, generating a reset event.
0 When read, this bit indicates that a MOSC failure has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
15:6
reserved
RO
0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
5
WDT1
R/W
-
Watchdog Timer 1 Reset
Value Description
1 When read, this bit indicates that Watchdog Timer 1 timed out
and generated a reset.
0 When read, this bit indicates that Watchdog Timer 1 has not
generated a reset since the previous power-on reset.
Writing a 0 to this bit clears it.
208
January 21, 2012
Texas Instruments-Production Data