LM3S1651 Datasheet, PDF (276/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

System Control
Register 37: Software Reset Control 0 (SRCR0), offset 0x040
This register allows individual modules to be reset. Writes to this register are masked by the bits in
the Device Capabilities 1 (DC1) register.
Software Reset Control 0 (SRCR0)
Base 0x400F.E000
Offset 0x040
Type R/W, reset 0x00000000
31
30
29
28
27
26
reserved
WDT1
Type RO
RO
RO
R/W
RO
RO
Reset
0
0
0
0
0
0
15
14
13
12
11
10
reserved
Type RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
25
24
23
reserved
RO
RO
RO
0
0
0
9
8
7
RO
RO
RO
0
0
0
22
21
20
19
18
17
16
PWM
reserved
ADC1 ADC0
RO
RO
R/W
RO
RO
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
HIB
reserved
WDT0
reserved
R/W
RO
RO
R/W
RO
RO
RO
0
0
0
0
0
0
0
Bit/Field
31:29
28
27:21
20
19:18
17
16
15:7
Name
reserved
WDT1
reserved
PWM
reserved
ADC1
ADC0
reserved
Type
RO
R/W
RO
R/W
RO
R/W
R/W
RO
Reset
0
0
0
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
WDT1 Reset Control
When this bit is set, Watchdog Timer module 1 is reset. All internal data
is lost and the registers are returned to their reset states. This bit must
be manually cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM Reset Control
When this bit is set, PWM module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC1 Reset Control
When this bit is set, ADC module 1 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
ADC0 Reset Control
When this bit is set, ADC module 0 is reset. All internal data is lost and
the registers are returned to their reset states. This bit must be manually
cleared after being set.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
276
January 21, 2012
Texas Instruments-Production Data