LM3S1651 Datasheet, PDF (11/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1651 Microcontroller
Figure 12-7. ADC Input Equivalency Diagram ......................................................................... 542
Figure 12-8. Internal Voltage Conversion Result ..................................................................... 543
Figure 12-9. External Voltage Conversion Result .................................................................... 544
Figure 12-10. Differential Sampling Range, V_{IN_ODD} = 1.5 V ...................................................... 545
Figure 12-11. Differential Sampling Range, V_{IN_ODD} = 0.75 V .................................................... 546
Figure 12-12. Differential Sampling Range, V_{IN_ODD} = 2.25 V .................................................... 546
Figure 12-13. Internal Temperature Sensor Characteristic ......................................................... 547
Figure 12-14. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 550
Figure 12-15. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 551
Figure 12-16. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 552
Figure 13-1. UART Module Block Diagram ............................................................................. 614
Figure 13-2. UART Character Frame ..................................................................................... 617
Figure 13-3. IrDA Data Modulation ......................................................................................... 619
Figure 13-4. LIN Message ..................................................................................................... 621
Figure 13-5. LIN Synchronization Field ................................................................................... 622
Figure 14-1. SSI Module Block Diagram ................................................................................. 678
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 682
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 682
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 683
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 683
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 684
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 685
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 685
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 686
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 687
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 688
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 688
Figure 15-1. I²C Block Diagram ............................................................................................. 720
Figure 15-2. I²C Bus Configuration ........................................................................................ 721
Figure 15-3. START and STOP Conditions ............................................................................. 722
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 722
Figure 15-5. R/S Bit in First Byte ............................................................................................ 723
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 723
Figure 15-7. Master Single TRANSMIT .................................................................................. 727
Figure 15-8. Master Single RECEIVE ..................................................................................... 728
Figure 15-9. Master TRANSMIT with Repeated START ........................................................... 729
Figure 15-10. Master RECEIVE with Repeated START ............................................................. 730
Figure 15-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 731
Figure 15-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 732
Figure 15-13. Slave Command Sequence ................................................................................ 733
Figure 16-1. I²S Block Diagram ............................................................................................. 758
Figure 16-2. I²S Data Transfer ............................................................................................... 761
Figure 16-3. Left-Justified Data Transfer ................................................................................ 761
Figure 16-4. Right-Justified Data Transfer .............................................................................. 761
Figure 17-1. Analog Comparator Module Block Diagram ......................................................... 794
Figure 17-2. Structure of Comparator Unit .............................................................................. 796
January 21, 2012
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