LM3S1651 Datasheet, PDF (770/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Inter-Integrated Circuit Sound (I²S) Interface
Register 1: I²S Transmit FIFO Data (I2STXFIFO), offset 0x000
This register is the 32-bit serial audio transmit data register. In Stereo mode, the data is written left,
right, left, right, and so on. The LRS bit in the I²S Transmit FIFO Configuration (I2STXFIFOCFG)
register can be read to verify the next position expected. In Compact 16-bit mode, bits [31:16] contain
the right sample, and bits [15:0] contain the left sample. In Compact 8-bit mode, bits [15:8] contain
the right sample, and bits [7:0] contain the left sample. In Mono mode, each 32-bit entry is a single
sample.
Note that if the FIFO is full and a write is attempted, a transmit FIFO write error is generated.
I2S Transmit FIFO Data (I2STXFIFO)
Base 0x4005.4000
Offset 0x000
Type WO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TXFIFO
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TXFIFO
Type WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
TXFIFO
Type
Reset Description
WO 0x0000.0000 TX Data
Serial audio sample data to be transmitted.
770
January 21, 2012
Texas Instruments-Production Data