LM3S1651 Datasheet, PDF (137/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1651 Microcontroller
Register 33: Application Interrupt and Reset Control (APINT), offset 0xD0C
Note: This register can only be accessed from privileged mode.
The APINT register provides priority grouping control for the exception model, endian status for
data accesses, and reset control of the system. To write to this register, 0x05FA must be written to
the VECTKEY field, otherwise the write is ignored.
The PRIGROUP field indicates the position of the binary point that splits the INTx fields in the
Interrupt Priority (PRIx) registers into separate group priority and subpriority fields. Table
3-8 on page 137 shows how the PRIGROUP value controls this split. The bit numbers in the Group
Priority Field and Subpriority Field columns in the table refer to the bits in the INTA field. For the
INTB field, the corresponding bits are 15:13; for INTC, 23:21; and for INTD, 31:29.
Note: Determining preemption of an exception uses only the group priority field.
Table 3-8. Interrupt Priority Levels
PRIGROUP Bit Field Binary Point^a
Group Priority Field Subpriority Field Group
Priorities
Subpriorities
0x0 - 0x4
bxxx.
[7:5]
None
8
1
0x5
bxx.y
[7:6]
[5]
4
2
0x6
bx.yy
[7]
[6:5]
2
4
0x7
b.yyy
None
[7:5]
1
8
a. INTx field showing the binary point. An x denotes a group priority field bit, and a y denotes a subpriority field bit.
Application Interrupt and Reset Control (APINT)
Base 0xE000.E000
Offset 0xD0C
Type R/W, reset 0xFA05.0000
31
30
29
28
27
26
25
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
0
1
24
23
VECTKEY
R/W
R/W
0
0
15
14
ENDIANESS
Type RO
RO
Reset
0
0
13
12
reserved
RO
RO
0
0
11
10
9
8
7
PRIGROUP
RO
R/W
R/W
R/W
RO
0
0
0
0
0
22
21
20
R/W
R/W
R/W
0
0
0
6
5
4
reserved
RO
RO
RO
0
0
0
19
18
17
16
R/W
R/W
R/W
R/W
0
1
0
1
3
2
1
0
SYSRESREQ VECTCLRACT VECTRESET
RO
WO
WO
WO
0
0
0
0
Bit/Field
31:16
15
14:11
Name
VECTKEY
ENDIANESS
reserved
Type
R/W
RO
RO
Reset
0xFA05
0
0x0
Description
Register Key
This field is used to guard against accidental writes to this register.
0x05FA must be written to this field in order to change the bits in this
register. On a read, 0xFA05 is returned.
Data Endianess
The Stellaris implementation uses only little-endian mode so this is
cleared to 0.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
January 21, 2012
137
Texas Instruments-Production Data