LM3S1651 Datasheet, PDF (301/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1651 Microcontroller
Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014
This register is the interrupt mask register for the Hibernation module interrupt sources. Each bit in
this register masks the corresponding bit in the Hibernation Raw Interrupt Status (HIBRIS) register.
If a bit is unmasked, the interrupt is sent to the interrupt controller. If the bit is masked, the interrupt
is not sent to the interrupt controller.
Hibernation Interrupt Mask (HIBIM)
Base 0x400F.C000
Offset 0x014
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
EXTW LOWBAT RTCALT1 RTCALT0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
Name
reserved
EXTW
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0
External Wake-Up Interrupt Mask
Value Description
1 An interrupt is sent to the interrupt controller when the EXTW bit
in the HIBRIS register is set.
0 The EXTW interrupt is suppressed and not sent to the interrupt
controller.
2
LOWBAT
R/W
0
Low Battery Voltage Interrupt Mask
Value Description
1 An interrupt is sent to the interrupt controller when the LOWBAT
bit in the HIBRIS register is set.
0 The LOWBAT interrupt is suppressed and not sent to the interrupt
controller.
1
RTCALT1
R/W
0
RTC Alert 1 Interrupt Mask
Value Description
1 An interrupt is sent to the interrupt controller when the RTCALT1
bit in the HIBRIS register is set.
0 The RTCALT1 interrupt is suppressed and not sent to the
interrupt controller.
January 21, 2012
301
Texas Instruments-Production Data