LM3S1651 Datasheet, PDF (899/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1651 Microcontroller
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024
This register provides the current set of interrupt sources that are asserted, regardless of whether
they cause an interrupt to be asserted to the controller (configured through the QEIINTEN register).
If a bit is set, the latched event has occurred; if a bit is clear, the event in question has not occurred.
QEI Raw Interrupt Status (QEIRIS)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x024
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
INTERROR INTDIR INTTIMER INTINDEX
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
2
1
Name
reserved
INTERROR
INTDIR
INTTIMER
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
0
Phase Error Detected
Value Description
1 A phase error has been detected.
0 An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTERROR bit in the QEIISC
register.
RO
0
Direction Change Detected
Value Description
1 The rotation direction has changed
0 An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTDIR bit in the QEIISC register.
RO
0
Velocity Timer Expired
Value Description
1 The velocity timer has expired.
0 An interrupt has not occurred.
This bit is cleared by writing a 1 to the INTTIMER bit in the QEIISC
register.
January 21, 2012
899
Texas Instruments-Production Data