LM3S1651 Datasheet, PDF (868/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Pulse Width Modulator (PWM)
Register 51: PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074
Register 52: PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4
Register 53: PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4
This register specifies which fault pin inputs are used to generate a fault condition. Each bit in the
following register indicates whether the corresponding fault pin is included in the fault condition. All
enabled fault pins are ORed together to form the PWMnFLTSRC0 portion of the fault condition.
The PWMnFLTSRC0 fault condition is then ORed with the PWMnFLTSRC1 fault condition to
generate the final fault condition for the PWM generator.
If the FLTSRC bit in the PWMnCTL register (see page 843) is clear, only the Fault0 signal affects
the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1
affect the fault condition generated.
PWM0 Fault Source 0 (PWM0FLTSRC0)
PWM0 base: 0x4002.8000
Offset 0x074
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
FAULT3 FAULT2 FAULT1 FAULT0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
2
Name
reserved
FAULT3
FAULT2
Type
RO
R/W
R/W
Reset
0x0000
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Fault3 Input
Value Description
0 The Fault3 signal is suppressed and cannot generate a fault
condition.
1 The Fault3 signal value is ORed with all other fault condition
generation inputs (Faultn signals and digital comparators).
Note: The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
Fault2 Input
Value Description
0 The Fault2 signal is suppressed and cannot generate a fault
condition.
1 The Fault2 signal value is ORed with all other fault condition
generation inputs (Faultn signals and digital comparators).
Note: The FLTSRC bit in the PWMnCTL register must be set for this
bit to affect fault condition generation.
868
January 21, 2012
Texas Instruments-Production Data