LM3S1651 Datasheet, PDF (21/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

Stellaris^® LM3S1651 Microcontroller
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GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 422
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 423
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 424
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 425
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 426
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 428
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 429
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 431
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 432
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 433
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 434
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 435
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 437
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 439
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 440
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 442
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 443
GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 445
GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 447
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 449
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 450
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 451
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 452
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 453
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 454
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 455
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 456
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 457
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 458
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 459
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 460
General-Purpose Timers ............................................................................................................. 461
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 478
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 479
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 481
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 483
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 486
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 488
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 491
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 494
Register 9: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 496
Register 10: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 497
Register 11: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 498
Register 12: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 499
Register 13: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 500
Register 14: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 501
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 502
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 503
January 21, 2012
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