LM3S1651 Datasheet, PDF (488/1033 Pages) Texas Instruments – ARM and Thumb are registered trademarks and Cortex is a trademark

General-Purpose Timers
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
GPTM Raw Interrupt Status (GPTMRIS)
Timer 0 base: 0x4003.0000
Timer 1 base: 0x4003.1000
Timer 2 base: 0x4003.2000
Timer 3 base: 0x4003.3000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
6
5
4
3
2
1
0
TBMRIS CBERIS CBMRIS TBTORIS
reserved
TAMRIS RTCRIS CAERIS CAMRIS TATORIS
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:12
11
10
Name
reserved
TBMRIS
CBERIS
Type
RO
RO
RO
Reset Description
0x0000.0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
GPTM Timer B Match Raw Interrupt
Value Description
1 The TBMIE bit is set in the GPTMTBMR register, and the match
values in the GPTMTBMATCHR and (optionally) GPTMTBPMR
registers have been reached when configured in one-shot or
periodic mode.
0 The match value has not been reached.
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR
register.
0
GPTM Timer B Capture Mode Event Raw Interrupt
Value Description
1 A capture mode event has occurred for Timer B. This interrupt
asserts when the subtimer is configured in Input Edge-Time
mode.
0 The capture mode event for Timer B has not occurred.
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR
register.
488
January 21, 2012
Texas Instruments-Production Data