SM320C6414-EP_16 Datasheet, PDF (87/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
URCLK
URDATA[7:0]
2
1
P48
H1
H2
H3
URADDR[4:0] N
0x1F
URCLAV
N
3
N+1
4
0x1F
5
N+1
N+2
7
8
6
0x1F
N+2
URENB
10
9
URSOC
11
12
† The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and URSOC
signals).
(1) The UTOPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLAV and
URSOC signals).
Figure 5-47. UTOPIA Slave Receive Timing ⁽¹⁾
5.14 TIMER TIMING
5.14.1 Timing Requirements for Timer Inputs⁽¹⁾ (see Figure 5-48)
NO.
1 t_w(TINPH) Pulse duration, TINP high
2
tw(TINPL)
Pulse duration, TINP low
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
NO.
PARAMETER
3
t_w(TOUTH)
Pulse duration, TOUT high
4
t_w(TOUTL)
Pulse duration, TOUT low
TINPx
TOUTx
2
1
4
3
Figure 5-48. Timer Timing
–50xEP
MIN
MAX
8P
8P
UNIT
ns
ns
–50xEP
MIN
MAX
8P-3
8P-3
UNIT
ns
ns
5.15 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING
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PARAMETER MEASUREMENT INFORMATION
87