SM320C6414-EP_16 Datasheet, PDF (4/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
www.ti.com
1.4.1 Device Characteristics
Table 1-1 provides an overview of the C6414, C6415, and C6416 DSPs. Table 1-1 shows significant
features of the C64x devices, including the capacity of on-chip RAM, the peripherals, the CPU frequency,
and the package type with pin count.
Table 1-1. Characteristics of the C6414, C6415, and C6416 Processors
HARDWARE FEATURES
EMIFA (64-bit bus width)
(default clock source = AECLKIN)
Peripherals
EMIFB (16-bit bus width)
(default clock source = BECLKIN)
Not all peripherals pins EDMA (64 independent channels)
are available at the same
time. (For more details,
HPI (32- or 16-bit user selectable)
see
the
Device PCI (32-bit) [DeviceID Register value 0xA106]
Configuration section.)
McBSPs
Peripheral performance is ^{(default internal clock source = CPU/4 clock frequency)}
dependent on chip-level _{UTOPIA (8-bit mode)}
configuration.
32-bit timers
(default internal clock source = CPU/8 clock frequency)
General-purpose input/output 0 (GP0)
Decoder coprocessors
VCP
TCP
Size (bytes)
On-chip memory
Organization
CPU ID + CPU Rev ID
Device_ID
Frequency
Cycle time
Voltage
PLL options
BGA package
Process technology
Product status
Control Status Register (CSR[31:16])
Silicon Revision Identification Register
(DEVICE_REV[19:16])
Address: 0x01B0 0200
MHz
ns
Core (V)
I/O (V)
CLKIN frequency multiplier
23 mm × 23 mm
CMOS
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
C6414, C6415, AND C6416
1
1
1
1 (HPI16 or HPI32)
1 (C6415/C6416 only)
3
1 (C6415/C6416 only)
3
16
1 (C6416 only)
1 (C6416 only)
1056K
16K-byte (16KB) L1 program (L1P) cache
16KB L1 data (L1D) cache
1024KB unified mapped RAM/cache (L2)
0x0C01
DEVICE_REV[19:16]
1111
0001
0010
Silicon revision
1.03 or earlier
1.03
1.1
500
2 ns (C6414-50A, C6415-50A, C6416-50A)
(500-MHz CPU, 100-MHz EMIF)⁽¹⁾
1.25 V (-50A)
3.3 V
Bypass (x1), x6, x12
532-pin BGA (GLZ)
0.3 µm
PD
(1) On these C64x devices, the rated EMIF speed affects only the SDRAM interface on EMIFA. For more detailed information, see the
EMIF Device Speed section of this data manual.
4
Introduction
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