SM320C6414-EP_16 Datasheet, PDF (47/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
3.1.3 Power-Supply Sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time (>1
second) if the other supply is below the proper operating voltage.
3.1.4 Power-Supply Design Considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and
I/O power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 3-3).
I/O Supply
Core Supply
Schottky
Diode
DV_DD
C6000
DSP
CV_DD
V_SS
GND
Figure 3-3. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
3.1.5 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for
the core supply and 30 for the I/O supply. These caps need to be close to the DSP, no more than 1.25-cm
maximum distance to be effective. Physically smaller caps are better, such as 0402, but need to be
evaluated from a yield/manufacturing point of view. Parasitic inductance limits the effectiveness of the
decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest
available capacitance value. As with the selection of any component, verification of capacitor availability
over the product's production lifetime should be considered.
3.1.6 IEEE 1149.1 JTAG Compatibility Statement
The TMS320C6414/15/16 DSP requires that both TRST and RESET be asserted upon power up to be
properly initialized. While RESET initializes the DSP core, TRST initializes the DSP emulation logic. Both
resets are required for proper operation.
While both TRST and RESET should be asserted upon power up, only RESET should be released for the
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port
interface and DSP emulation logic in the reset state.
TRST only should be released when it is necessary to use a JTAG controller to debug the DSP or
exercise the DSP boundary scan functionality.
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