SM320C6414-EP_16 Datasheet, PDF (79/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
5.11.1 Timing Requirements for PCLK ^{(1) (2)}(see Figure 5-36
NO.
PARAMETER
–50xEP
1
t_c(PCLK)
Cycle time, PCLK
2
t_w(PCLKH)
Pulse duration, PCLK high
3
t_w(PCLKL)
Pulse duration, PCLK low
4
t_sr(PCLK)
Δv/Δt slew rate, PCLK
MIN
30 (or 8P⁽³⁾)
11
11
1
(1) For 3.3-V operation, the reference points for the rise and fall transitions are measured at V_ILP MAX and V_IHP MIN.
(2) P = 1/CPU clock frequency in ns. For example when running parts at 500 MHz, use P = 2 ns.
(3) Select the parameter value of 30 ns or 8P, whichever is greater.
MAX
4
UNIT
ns
ns
ns
V/ns
1
4
2
0.4 DV_DD V MIN
Peak to Peak for
3.3V signaling
PCLK
3
4
Figure 5-36. PCLK Timing
5.11.2 Timing Requirements for PCI Reset (see Figure 5-37)
NO.
1
t_w(PRST)
2
t_{su(PCLKA-PRSTH)}
Pulse duration, PRST
Setup time, PCLK active before PRST high
PCLK
1
PRST
2
Figure 5-37. PCI Reset (PRST) Timing
–50xEP
MIN
1
100
MAX
UNIT
ms
µs
5.11.3 Timing Requirements for PCI Inputs (see Figure 5-38)
NO.
1
2
NO.
t_su(IV-PCLKH)
t_h(IV-PCLKH)
Setup time, input valid before PCLK high
Hold time, input valid after PCLK high
PARAMETER
1
t_d(PCLKH-OV)
2
t_d(PCLKH-OIV)
3
t_d(PCLKH-OLZ)
4
t_d(PCLKH-OHZ)
Delay time, PCLK high to output valid
Delay time, PCLK high to output invalid
Delay time, PCLK high to output low impedance
Delay time, PCLK high to output high impedance
–50xEP
MIN MAX
7
0
UNIT
ns
ns
–50xEP
MIN MAX
11
2
2
28
UNIT
ns
ns
ns
ns
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PARAMETER MEASUREMENT INFORMATION
79