SM320C6414-EP_16 Datasheet, PDF (56/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
5
6
ECLKIN
1
ECLKOUT2
3
2
4
Figure 5-10. ECLKOUT2 Timing for EMIFA and EMIFB Modules
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4
5.2 ASYNCHRONOUS MEMORY TIMING
5.2.1 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module ^{(1) (2) (3)}
(see Figure 5-11 and Figure 5-12)
NO.
PARAMETER
–50xEP
MIN
MAX
UNIT
3
t_su(EDV-AREH)
Setup time, EDx valid before ARE high
4
t_h(AREH-EDV)
Hold time, EDx valid after ARE high
6
t_{su(ARDY-EKO1H)} Setup time, ARDY valid before ECLKOUT1 high
7
t_{h(EKO1H-ARDY)}
Hold time, ARDY valid after ECLKOUT1 high
6.5
ns
1
ns
3
ns
1.5
ns
(1) To ensure data setup time, program the strobe width wide enough. ARDY is internally synchronized. The ARDY is recognized in the
cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of ARDY signal should be wide
enough (e.g., pulse width = 2E) to ensure setup and hold time is met.o
(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters
are programmed via the EMIF CE space control registers.
(3) These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an A and all EMIFB signals are prefixed by
a B. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix A or B may be omitted [e.g., the
asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA)
and BAOE, BARE, and BAWE (for EMIFB)].
NO.
PARAMETER
1 t_{osu(SELV-AREL)} Output setup time, select signals valid to ARE low
2 t_{oh(AREH-SELIV)} Output hold time, ARE high to select signals invalid
5 t_{d(EKO1H-AREV)} Delay time, ECLKOUT1 high to ARE valid
8 t_{osu(SELV-AWEL)} Output setup time, select signals valid to AWE low
9 t_{oh(AWEH-SELIV)} Output hold time, AWE high to select signals invalid
10 t_{d(EKO1H-AWEV)} Delay time, ECLKOUT1 high to AWE valid
–50xEP
MIN
RS × E-1.5
RH × E-1.9
1
WS × E-1.7
WH × E-1.8
1.3
MAX
7
7.1
UNIT
ns
ns
ns
ns
ns
ns
5.2.3 Timing Requirements for Asynchronous Memory Cycles for EMIFB Module ^{(1) (2) (3)}
(see Figure 5-11 and Figure 5-12)
NO.
3
t_su(EDV-AREH)
4
t_h(AREH-EDV)
PARAMETER
Setup time, EDx valid before ARE high
Hold time, EDx valid after ARE high
–50xEP
MIN MAX
6.2
1
UNIT
ns
ns
(1) To ensure data setup time, program the strobe width wide enough. ARDY is internally synchronized. The ARDY is recognized in the
cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of ARDY signal should be wide
enough (e.g., pulse width = 2E) to ensure setup and hold time is met.o
(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters
are programmed via the EMIF CE space control registers.
(3) These C64x devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an A and all EMIFB signals are prefixed by
a B. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix A or B may be omitted [e.g., the
asynchronous memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA)
and BAOE, BARE, and BAWE (for EMIFB)].
56
PARAMETER MEASUREMENT INFORMATION
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