SM320C6414-EP_16 Datasheet, PDF (53/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external
device and from the external device to the DSP. This round-trip delay tends to negatively impact the input
setup time margin, but also tends to improve the input hold time margins (see Table 5-1 and Figure 5-4).
Figure 5-4 represents a general transfer between the DSP and an external device. The figure also
represents board route delays and how they are perceived by the DSP and the external device.
Table 5-1. Board-Level Timing (see Figure 5-4)
NO.
DESCRIPTION
1
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
4
External device hold time requirement
5
External device setup time requirement
6
Control signal route delay
7
External device hold time
8
External device access time
9
DSP hold time requirement
10
DSP setup time requirement
11
Data route delay
ECLKOUTx
(Output from DSP)
ECLKOUTx
(Input to External Device)
Control Signals^†
(Output from DSP)
Control Signals
(Input to External Device)
Data Signals^‡
(Output from External Device)
Data Signals^‡
(Input to DSP)
1
2
3
4
5
6
7
8
9
10
11
Figure 5-4. Board-Level Input/Output Timing
5.1 INPUT AND OUTPUT CLOCKS
5.1.1 Timing Requirements for CLKIN for –50xEP Devices^{(1) (2) (3)} (see Figure 5-5)
NO.
1
t_c(CLKIN)
Cycle time, CLKIN
PLL MODE x12
MIN MAX
24 33.3
–50xEP
PLL MODE x6
MIN MAX
13.3 33.3
x1 (BYPASS)
MIN MAX
13.3 33.3
UNIT
ns
(1) The reference points for the rise and fall transitions are measured at V_IL MAX and V_IH MIN.
(2) For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data manual.
(3) C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
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PARAMETER MEASUREMENT INFORMATION
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