SM320C6414-EP_16 Datasheet, PDF (17/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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HEX ADDRESS
0x3400 0000–0x37FF
FFFF
019C 0008
019C 000C
019C 0010
019C 0014
019C 0018
019C 001C
019C 0020
019C 0024
019C 0028
019C 002C
019C 0030
019C 0034
019C 0038
019C 003C
019C 0040–0193 FFFF
SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
Table 1-13. McBSP 1 Registers (continued)
ACRONYM
REGISTER NAME
COMMENTS
DXR1
McBSP1 Data Transmit Register via peripheral bus
SPCR1
RCR1
XCR1
SRGR1
MCR1
RCERE01
XCERE01
PCR1
RCERE11
XCERE11
RCERE21
XCERE21
RCERE31
XCERE31
–
McBSP1 Serial Port Control Register
McBSP1 Receive Control Register
McBSP1 Transmit Control Register
McBSP1 Sample Rate Generator Register
McBSP1 Multichannel Control Register
McBSP1 Enhanced Receive Channel Enable Register
0
McBSP1 Enhanced Transmit Channel Enable Register
0
McBSP1 Pin Control Register
McBSP1 Enhanced Receive Channel Enable Register
1
McBSP1 Enhanced Transmit Channel Enable Register
1
McBSP1 Enhanced Receive Channel Enable Register
2
McBSP1 Enhanced Transmit Channel Enable Register
2
McBSP1 Enhanced Receive Channel Enable Register
3
McBSP1 Enhanced Transmit Channel Enable Register
3
Reserved
HEX ADDRESS
ACRONYM
Table 1-14. McBSP 2 Registers
REGISTER NAME
01A4 0000
DRR2 McBSP2 Data Receive Register via configuration bus
0x3800 0000–0x3BFF FFFF
01A4 0004
0x3800 0000–0x3BFF FFFF
01A4 0008
01A4 000C
01A4 0010
01A4 0014
01A4 0018
01A4 001C
01A4 0020
01A4 0024
01A4 0028
01A4 002C
01A4 0030
01A4 0034
01A4 0038
01A4 003C
01A4 0040–01A7 FFFF
DRR2
DXR2
DXR2
SPCR2
RCR2
XCR2
SRGR2
MCR2
RCERE02
XCERE02
PCR2
RCERE12
XCERE12
RCERE22
XCERE22
RCERE32
XCERE32
–
McBSP2 Data Receive Register via peripheral bus
McBSP2 Data Transmit Register via configuration bus
McBSP2 Data Transmit Register via peripheral bus
McBSP2 Serial Port Control Register
McBSP2 Receive Control Register
McBSP2 Transmit Control Register
McBSP2 Sample Rate Generator Register
McBSP2 Multichannel Control Register
McBSP2 Enhanced Receive Channel Enable Register 0
McBSP2 Enhanced Transmit Channel Enable Register 0
McBSP2 Pin Control Register
McBSP2 Enhanced Receive Channel Enable Register 1
McBSP2 Enhanced Transmit Channel Enable Register 1
McBSP2 Enhanced Receive Channel Enable Register 2
McBSP2 Enhanced Transmit Channel Enable Register 2
McBSP2 Enhanced Receive Channel Enable Register 3
McBSP2 Enhanced Transmit Channel Enable Register 3
Reserved
COMMENTS
The CPU and EDMA controller can
only read this register; they cannot
write to it.
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Introduction
17