SM320C6414-EP_16 Datasheet, PDF (18/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
www.ti.com
HEX ADDRESS
0194 0000
0194 0004
0194 0008
0194 000C–0197 FFFF
ACRONYM
CTL0
PRD0
CNT0
–
Table 1-15. Timer 0 Registers
REGISTER NAME
Timer 0 Control
Timer 0 Period
Timer 0 Counter
Reserved
COMMENTS
Determines the operating mode of the timer, monitors the timer status,
and controls the function of the TOUT pin
Contains the number of timer input clock cycles to count. This number
controls the TSTAT signal frequency.
Contains the current value of the incrementing counter
HEX ADDRESS
0198 0000
0198 0004
0198 0008
0198 000C–019B FFFF
Table 1-16. Timer 1 Registers
ACRONYM REGISTER NAME
CTL1
Timer 1 Control
PRD1 Timer 1 Period
CNT1
–
Timer 1 Counter
Reserved
COMMENTS
Determines the operating mode of the timer, monitors the timer status,
and controls the function of the TOUT pin
Contains the number of timer input clock cycles to count. This number
controls the TSTAT signal frequency.
Contains the current value of the incrementing counter
Table 1-17. Timer 2 Registers
HEX ADDRESS
01AC 0000
ACRONYM
REGISTER NAME
CTL2
Timer 2 Control
01AC 0004
01AC 0008
01AC 000C–01AF FFFF
PRD2
CNT2
–
Timer 2 Period
Timer 2 Counter
Reserved
COMMENTS
Determines the operating mode of the timer, monitors the timer status,
and controls the function of the TOUT pin
Contains the number of timer input clock cycles to count. This number
controls the TSTAT signal frequency.
Contains the current value of the incrementing counter
Table 1-18. HPI Registers
HEX ADDRESS
–
0188 0000
0188 0004
0188 0008
0188 000C–0189 FFFF
018A 0000
018A 0004–018B FFFF
ACRONYM
HPID
HPIC
HPIA (HPIAW)⁽¹⁾
HPIA (HPIAR)⁽¹⁾
–
TRCTL
–
REGISTER NAME
HPI Data
HPI Control
HPI Address (Write)
HPI Address (Read)
Reserved
HPI Transfer Request Control
Reserved
COMMENTS
Host read/write access only
HPIC has both host/CPU read/write access.
HPIA has both host/CPU read/write access.
(1) Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR
independently.
HEX ADDRESS
01B0 0000
01B0 0004
01B0 0008
01B0 000C
01B0 0010
01B0 0014
01B0 0018
01B0 001C
ACRONYM
GPEN
GPDIR
GPVAL
–
GPDH
GPHM
GPDL
GPLM
Table 1-19. GPIO Registers
GPIO Enable
GPIO Direction
GPIO Value
Reserved
GPIO Delta High
GPIO High Mask
GPIO Delta Low
GPIO Low Mask
REGISTER NAME
18
Introduction
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