SM320C6414-EP_16 Datasheet, PDF (35/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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2.5 Terminal Functions
SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
TERMINAL
NAME
NO.
TYPE ⁽¹⁾
IPD/IPU
(2)
DESCRIPTION
CLOCK/PLL Configuration
CLKIN
H4
I
IPD Clock input. This clock is the input to the on-chip PLL.
CLKOUT4/GP1⁽³⁾ AE6 I/O/Z
IPD
Clock output at 1/4 of the device speed (O/Z) (default) or this pin can be programmed as a
GPIO1 pin (I/O/Z).
CLKOUT6/GP2⁽³⁾ AD6 I/O/Z
IPD
Clock output at 1/6 of the device speed (O/Z) (default) or this pin can be programmed as a
GPIO2 pin (I/O/Z).
CLKMODE1
CLKMODE0
PLLV ⁽⁴⁾
G1
I
IPD Clock-mode select. Selects whether the CPU clock frequency = input clock frequency ×1
(bypass), ×6, or ×12.
H2
I
IPD ^{For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL}
section of this data manual.
J6
A ⁽⁵⁾
PLL voltage supply
JTAG Emulation
TMS
AB16
I
IPU JTAG test-port mode select
TDO
AE19 O/Z
IPU JTAG test-port data out
TDI
AF18
I
IPU JTAG test-port data in
TCK
AF16
I
IPU JTAG test-port clock
TRST
AB15
I
IPD
JTAG test-port reset. For IEEE Std 1149.1 JTAG compatibility, see the IEEE Std 1149.1
JTAG Compatibility Statement section of this data manual.
EMU11
AC18
EMU10
AD18
EMU9
AE18
EMU8
AC17
EMU7
EMU6
AF17
I/O/Z
AD17
IPU Emulation pin [11:2]. Reserved for future use, leave unconnected.
EMU5
AE17
EMU4
AC16
EMU3
AD16
EMU2
AE16
Emulation pins [1:0]
Select the device functional mode of operation:
EMU[1:0]
Operation
EMU1
EMU0
AC15
AF15
I/O/Z
IPU
00
Boundary Scan/Normal mode (see Note)
01
Reserved
10
Reserved
11
Emulation/Normal mode (default) (see the IEEE 1149.1 JTAG
Compatibility Statement section of this data manual)
Normal mode refers to the DSPs normal operational mode, when the DSP is free running.
The DSP can be placed in normal operational mode when the EMU[1:0] pins are configured
for either Boundary Scan or Emulation.
Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal
pulldown (IPD) on the TRST signal must not be opposed in order to operate in Normal
mode.
For the Boundary Scan mode pulldown EMU[1:0] pins with a dedicated 1-kΩ resistor.
Resets, Interrupts, and General-Purpose Input/Outputs (GPIOs)
RESET
AC7
I
Device reset
NMI
B4
I
IPD Nonmaskable interrupt, edge-driven (rising edge)
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
(2) IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the
opposite supply rail, a 1-kΩ resistor should be used.)
(3) These pins are multiplexed pins. For more details, see the Device Configurations section of this data manual.
(4) PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
(5) A = Analog signal (PLL filter)
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Device Configurations
35