SM320C6414-EP_16 Datasheet, PDF (72/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
ECLKOUT1
ABUSREQ
BBUSREQ
1
1
2
2
Figure 5-25. BUSREQ Timing for EMIFA and EMIFB
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5.8 RESET TIMING
5.8.1 Timing Requirements for Reset⁽¹⁾ (see Figure 5-26 )
NO.
PARAMETER
–50xEP
UNIT
MIN MAX
1 t_w(RST) Width of the RESET pulse
PLL stable⁽²⁾
PLL needs to sync up⁽³⁾
10P
ns
250
µs
16 t_su(boot) Setup time, boot configuration bits valid before RESET high⁽⁴⁾
17 t_h(boot) Hold time, boot configuration bits valid after RESET high⁽⁴⁾
4P
ns
4P
ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
(2) This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x6, x12 when CLKIN and PLL are stable.
(3) This parameter applies to CLKMODE x6, x12 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to
the clock PLL circuit. The PLL, however, may need up to 250 ＝s to stabilize following device power up or after PLL configuration has
been changed. During that time, RESET must be asserted to ensure proper device operation. See the clock PLL section for PLL lock
times.
(4) EMIFB address pins BEA[20:13, 11, 7] are the boot-configuration pins during device reset.
NO.
PARAMETER
2
t_d(RSTL-ECKI)
Delay time, RESET low to ECLKIN synchronized internally
3
t_d(RSTH-ECKI)
Delay time, RESET high to ECLKIN synchronized internally
4 t_{d(RSTL-ECKO1HZ)} Delay time, RESET low to ECLKOUT1 high impedance
5
t_{d(RSTH-ECKO1V)}
Delay time, RESET high to ECLKOUT1 valid
6
t_{d(RSTL-EMIFZHZ)}
Delay time, RESET low to EMIF Z high impedance
7
t_{d(RSTH-EMIFZV)}
Delay time, RESET high to EMIF Z valid
8
t_{d(RSTL-EMIFHIV)}
Delay time, RESET low to EMIF high group invalid
9
t_{d(RSTH-EMIFHV)}
Delay time, RESET high to EMIF high group valid
10 t_{d(RSTL-EMIFLIV)}
Delay time, RESET low to EMIF low group invalid
11 t_{d(RSTH-EMIFLV)}
Delay time, RESET high to EMIF low group valid
12 t_{d(RSTL-LOWIV)}
Delay time, RESET low to low group invalid
13 t_d(RSTH-LOWV)
Delay time, RESET high to low group valid
14 t_d(RSTL-ZHZ)
Delay time, RESET low to Z group high impedance
15 t_d(RSTH-ZV)
16 t_d(PCLK-RSTH)
Delay time, RESET high to Z group valid
Delay time, PCLK active to RESET high ⁽³⁾
–50xEP
MIN
MAX
2E 3P + 20E
2E 8P + 20E
2E
8P + 20E
2E 3P + 4E
16E 8P + 20E
2E
8P + 20E
2E
8P + 20E
0
11P
0
2P
8P
32N
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
72
PARAMETER MEASUREMENT INFORMATION
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