SM320C6414-EP_16 Datasheet, PDF (21/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
Table 1-24. TCP Registers (C6414 Only) (continued)
HEX ADDRESS
EDMA BUS
PERIPHERAL BUS
–
01BA 0040
–
01BA 0050
–
01BA 0058
ACRONYM
TCPEND
TCPERR
TCPSTAT
TCP Endian
TCP Error
TCP Status
REGISTER
1.4.7 EDMA Channel Synchronization Events
The C64x EDMA supports up to 64 EDMA channels that service peripheral devices and external memory.
Table 1-25 lists the source of C64x EDMA synchronization events associated with each of the
programmable EDMA channels. For the C64x device, the association of an event to a channel is fixed;
each of the EDMA channels has one specific event associated with it. These specific events are captured
in the EDMA event registers (ERL, ERH), even if the events are disabled by the EDMA event enable
registers (EERL, EERH). The priority of each event can be specified independently in the transfer
parameters stored in the EDMA parameter RAM. For more detailed information on the EDMA module and
how EDMA events are enabled, captured, processed, linked, chained, and cleared, etc., see the EDMA
Controller chapter of the TMS320C6000 Peripherals Reference Guide (literature number SPRU190).
EDMA
CHANNEL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22–27
28
Table 1-25. SM320C64x EDMA Channel Synchronization Events⁽¹⁾
EVENT NAME
DSP_INT
TINT0
TINT1
SD_INTA
GPINT4/EXT_INT4
GPINT5/EXT_INT5
GPINT6/EXT_INT6
GPINT7/ EXT_INT7
GPINT0
GPINT1
GPINT2
GPINT3
XEVT0
REVT0
XEVT1
REVT1
–
XEVT2
REVT2
TINT2
SD_INTB
–
–
VCPREVT
EVENT DESCRIPTION
HPI/PCI-to-DSP interrupt (PCI peripheral supported on C6415 and C6416 only)⁽²⁾
Timer 0 interrupt
Timer 1 interrupt
EMIFA SDRAM timer interrupt
GPIO event 4/External interrupt pin 4
GPIO event 5/External interrupt pin 5
GPIO event 6/External interrupt pin 6
GPIO event 7/External interrupt pin 7
GPIO event 0
GPIO event 1
GPIO event 2
GPIO event 3
McBSP0 transmit event
McBSP0 receive event
McBSP1 transmit event
McBSP1 receive event
None
McBSP2 transmit event
McBSP2 receive event
Timer 2 interrupt
EMIFB SDRAM timer interrupt
Reserved, for future expansion
None
VCP receive event (C6416 only)⁽³⁾
(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate
transfer completion events. For more detailed information on EDMA event-transfer chaining, see the EDMA Controller chapter of the
TMS320C6000 Peripherals Reference Guide (SPRU190).
(2) The PCI and UTOPIA peripherals are not supported on the C6414 device; therefore, these EDMA synchronization events are reserved.
(3) The VCP/TCP EDMA synchronization events are supported on the C6416 only. For the C6414 and C6415 devices, these events are
reserved.
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Introduction
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