SM320C6414-EP_16 Datasheet, PDF (46/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
3.3 V
EMI
filter
C1 C2
10 µF 0.1 µF
PLLV
CLKMODE0
CLKMODE1
CLKIN
PLLMULT
PLL
x6, x12
PLLCLK 1
0
www.ti.com
CPU Clock
/2
Peripheral Bus
/8
Timer Internal Clock
/4
CLKOUT4,
McBSP Internal Clock
/6
CLKOUT6
00 01 10
ECLKIN_SEL (DEVCFG.[17,16]
and DEVCFG.[15,14])
/4
ECLKIN
Internal to C64x
/2
EMIF
00 01 10
EK2RATE
(GBLCTL.[19,18])
(For the PLL Options, CLKMODE Pins Setup, and
PLL Clock Frequency Ranges, see NO TAG.)
ECLKOUT1 ECLKOUT2
A. Place all PLL external components (C1, C2, and the EMI filter) as close to the C6000 DSP device as possible. For the
best performance, TI recommends that all the PLL external components be on a single side of the board without
jumpers, switches, or components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2,
and the EMI Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV_DD.
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 3-2. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
Table 3-2. SM320C64x PLL Multiply Factor Options, Clock Frequency Ranges, and Typical Lock Time^{(1) (2)}
CLKMODE1 CLKMODE0
0
0
0
1
1
0
1
1
GLZ PACKAGE-23 × 23-mm BGA
CLKMODE
(PLL MULTIPLY
FACTORS)
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
Bypass (x1)
30–75
30–75
x6
30–75
180–450
x12
30–60
360–720
Reserved
–
–
CLKOUT4
RANGE
(MHz)
7.5–18.8
45–112.5
90–180
–
CLKOUT6
RANGE
(MHz)
5–12.5
30–75
60–120
–
TYPICAL LOCK
TIME (ms)⁽³⁾
N/A
75
–
(1) These clock frequency range values are applicable to a 600-MHz CPU, 133-MHz EMIFA speed device. For a 500-MHz CPU, 100-MHz
EMIF, and 700-MHz CPU, 100 MHz EMIF device speed values, see the CLKIN timing requirements table for the specific device speed.
(2) Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the C64x device to one of the valid PLL
multiply clock
(3) Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For
example, if the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
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