SM320C6414-EP_16 Datasheet, PDF (14/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
HEX ADDRESS
0184 82D8
0184 82DC
0184 82E0
0184 82E4
0184 82E8
0184 82EC
0184 82F0
0184 82F4
0184 82F8
0184 82FC
0184 8300–0184 83FC
0184 8400–0187 FFFF
Table 1-6. L2 Cache Registers (continued)
ACRONYM
MAR182
MAR183
MAR184
MAR185
MAR186
MAR187
MAR188
MAR189
MAR190
MAR191
MAR192 to MAR255
–
REGISTER NAME
Controls EMIFA CE3 range B600 0000–B6FF FFFF
Controls EMIFA CE3 range B700 B000–B7FF FFFF
Controls EMIFA CE3 range B800 0000–B8FF FFFF
Controls EMIFA CE3 range B900 0000–B9FF FFFF
Controls EMIFA CE3 range BA00 0000–BAFF FFFF
Controls EMIFA CE3 range BB00 0000–BBFF FFFF
Controls EMIFA CE3 range BC00 0000–BCFF FFFF
Controls EMIFA CE3 range BD00 0000–BDFF FFFF
Controls EMIFA CE3 range BE00 0000–BEFF FFFF
Controls EMIFA CE3 range BF00 B000–BDFF FFFF
Reserved
Reserved
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HEX ADDRESS
01A0 FF9C
01A0 FFA4
01A0 FFA8
01A0 FFAC
01A0 FFB0
01A0 FFB4
01A0 FFB8
01A0 FFBC
01A0 FFC0
01A0 FFC4
01A0 FFC8
01A0 FFCC
01A0 FFDC
01A0 FFE0
01A0 FFE4
01A0 FFE8
01A0 FFEC
01A0 FFF0
01A0 FFF4
01A0 FFF8
01A0 FFFC
01A1 0000–01A3 FFFF
Table 1-7. EDMA Registers
ACRONYM
EPRH
CIPRH
CIERH
CCERH
ERH
EERH
ECRH
ESRH
PQAR0
PQAR1
PQAR2
PQAR3
EPRL
PQSR
CIPRL
CIERL
CCERL
ERL
EERL
ECRL
ESRL
–
REGISTER NAME
Event Polarity High Register
Channel Interrupt Pending High Register
Channel Interrupt Enable High Register
Channel Chain Enable High Register
Event High Register
Event Enable High Register
Event Clear High Register
Event Set High Register
Priority Queue Allocation Register 0
Priority Queue Allocation Register 1
Priority Queue Allocation Register 2
Priority Queue Allocation Register 3
Event Polarity Low Register
Priority Queue Status Register
Channel Interrupt Pending Low Register
Channel Interrupt Enable Low Register
Channel Chain Enable Low Register
Event Low Register
Event Enable Low Register
Event Clear Low Register
Event Set Low Register
Reserved
Table 1-8. EDMA Parameter RAM⁽¹⁾
HEX ADDRESS
01A0 0000–01A0 0017
01A0 0018–01A0 002F
01A0 0030–01A0 0047
01A0 0048–01A0 005F
01A0 0060—01A0 0077
01A0 0078–01A0 008F
Parameters for Event 0 (6 words)
Parameters for Event 1 (6 words)
Parameters for Event 2 (6 words)
Parameters for Event 3 (6 words)
Parameters for Event 4 (6 words)
Parameters for Event 5 (6 words)
REGISTER NAME
(1) The C64x device has 21 parameter sets (6 words each) that can be used to reload/link EDMA transfers.
14
Introduction
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