SM320C6414-EP_16 Datasheet, PDF (74/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
5.9 EXTERNAL INTERRUPT TIMING
5.9.1 Timing Requirements for External Interrupts⁽¹⁾ (see Figure 5-27)
NO.
PARAMETER
1
t_w(ILOW)
Width of the NMI interrupt pulse low
Width of the EXT_INT interrupt pulse low
Width of the NMI interrupt pulse high
2
t_w(IHIGH)H
Width of the EXT_INT interrupt pulse high
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
EXT_INTx, NMI
2
1
Figure 5-27. External/NMI Interrupt Timing
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–50xEP
MIN MAX
4P
8P
4P
8P
UNIT
ns
ns
ns
ns
5.10 HOST-PORT INTERFACE (HPI)
5.10.1 Timing Requirements for Host-Port Interface Cycles^{(1) (2)} (see Figure 5-28 through
Figure 5-35)
NO.
1
t_{su(SELV-HSTBL)}
2
t_{h(HSTBL-SELV)}
3
t_w(HSTBL)
4
t_w(HSTBH)
10 t_{su(SELV-HASL)}
11 t_h(HASL-SELV)
12 t_{su(HDV-HSTBH)}
13 t_h(HSTBH-HDV)
14 t_{h(HRDYL-HSTBL)}
PARAMETER
Setup time, select signals⁽³⁾ valid before HSTROBE low
Hold time, select signals⁽³⁾ valid after HSTROBE low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals⁽³⁾ valid before HAS low
Hold time, select signals⁽³⁾ valid after HAS low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
–50xEP
MIN MAX
5
2.4
4P ⁽⁴⁾
4P
5
2
5
2.8
2
18 t_{su(HASL-HSTBL)}
Setup time, HAS low before HSTROBE low
2
19 t_{h(HSTBL-HASL)}
Hold time, HAS low after HSTROBE low
2.1
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT (HDS1 XOR HDS2)] OR HCS.
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 500 MHz, use P = 2 ns.
(3) Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
(4) Select the parameter value of 4P or 12.5 ns, whichever is greater.
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NO.
6
t_{d(HSTBL-HRDYH)}
7
t_{d(HSTBL-HDLZ)}
8
t_d(HDV-HRDYL)
9
t_{oh(HSTBH-HDV)}
PARAMETER
Delay time, HSTROBE low to HRDY high⁽¹⁾
Delay time, HSTROBE low to HD low impedance for an HPI read
Delay time, HD valid to HRDY low
Output hold time, HD valid after HSTROBE high
–50xEP
MIN
MAX
1.3
4P + 9
2
–3
1.5
UNIT
ns
ns
ns
ns
(1) This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word
transfer (HPI16) on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and
HRDY remains high until the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes
high if the internal write buffer is full.
74
PARAMETER MEASUREMENT INFORMATION
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