SM320C6414-EP_16 Datasheet, PDF (23/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

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SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
1.4.8 Interrupt Sources and Interrupt Selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 1-26. The highest-priority
interrupt is INT_00 (dedicated to RESET), while the lowest-priority interrupt is INT_15. The first four
interrupts (INT_00–INT_03) are nonmaskable and fixed. The remaining interrupts (INT_04–INT_15) are
maskable and default to the interrupt source specified in Table 1-26. The interrupt source for interrupts
4–15 can be programmed by modifying the selector value (binary value) in the corresponding fields of the
interrupt selector control registers; MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
Table 1-26. C64x DSP Interrupts
CPU
INTERRUPT
NUMBER
INT_00 ⁽¹⁾
INT_01 ⁽¹⁾
INT_02 ⁽¹⁾
INT_03 ⁽¹⁾
INT_04 ⁽²⁾
INT_05 ⁽²⁾
INT_06 ⁽²⁾
INT_07 ⁽²⁾
INT_08 ⁽²⁾
INT_09 ⁽²⁾
INT_10 ⁽²⁾
INT_11 ⁽²⁾
INT_12 ⁽²⁾
INT_13 ⁽²⁾
INT_14 ⁽²⁾
INT_15 ⁽²⁾
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
INTERRUPT
SELECTOR
CONTROL
REGISTER
–
–
–
–
MUXL[4:0]
MUXL[9:5]
MUXL[14:10]
MUXL[20:16]
MUXL[25:21]
MUXL[30:26]
MUXH[4:0]
MUXH[9:5]
MUXH[14:10]
MUXH[20:16]
MUXH[25:21]
MUXH[30:26]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT
INTERRUPT SOURCE
–
–
–
00100
00101
00110
00111
01000
01001
00011
01010
01011
00000
00001
00010
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000–11101
11110
11111
RESET
NMI
Reserved
Reserved
GPINT4/EXT_INT4
GPINT5/EXT_INT5
GPINT6/EXT_INT6
GPINT7/EXT_INT7
EDMA_INT
EMU_DTDMA
SD_INTA
EMU_RTDXRX
EMU_RTDXTX
DSP_INT
TINT0
TINT1
XINT0
RINT0
XINT1
RINT1
GPINT0
XINT2
RINT2
TINT2
SD_INTB
Reserved
Reserved
UINT
Reserved
VCPINT
TCPINT
Reserved. Do not use.
GPIO interrupt 4/external interrupt 4
GPIO interrupt 5/external interrupt 5
TCP interrupt (C6416 only)
GPIO interrupt 6/external interrupt 6
GPIO interrupt 7/external interrupt 7
EDMA channel (0–63) interrupt
EMU DTDMA
EMIFA SDRAM timer interrupt
EMU real-time data exchange (RTDX) receive
EMU RTDX transmit
HPI/PCI-to-DSP interrupt (PCI supported on C6415 and C6416
only)
Timer 0 interrupt
Timer 1 interrupt
McBSP0 transmit interrupt
McBSP0 receive interrupt
McBSP1 transmit interrupt
McBSP1 receive interrupt
GPIO interrupt 0
McBSP2 transmit interrupt
McBSP2 receive interrupt
Timer 2 interrupt
EMIFB SDRAM timer interrupt
Reserved. Do not use.
Reserved. Do not use.
UTOPIA interrupt (C6415/C6416 only)
Reserved. Do not use.
VCP interrupt (C6416 only)
TCP interrupt (C6416 only)
(1) Interrupts INT_00–INT_03 are nonmaskable and fixed.
(2) Interrupts INT_04–INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.
Table 1-26 shows the default interrupt sources for interrupts INT_04–INT_15. For more detailed information on interrupt sources and
selection, see the Interrupt Selector and External Interrupts chapter of the TMS320C6000 Peripherals Reference Guide (SPRU190).
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