SM320C6414-EP_16 Datasheet, PDF (6/93 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSORS

SM320C6414-EP, SM320C6415-EP, SM320C6416-EP
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008
www.ti.com
For more detailed information on the device compatibility and similarities/differences among the C6414,
C6415, and C6416 devices, see the How To Begin Development Today With the TMS320C6414,
TMS320C6415, and TMS320C6416 DSPs application report (literature number SPRA718).
1.4.3 Functional Block and CPU (DSP Core) Diagram
VCP^(A)
SDRAM
SBSRAM
ZBT SRAM
FIFO
TCP^(A)
64
EMIF A
16
EMIF B
Timer 2
SRAM
ROM/FLASH
Timer 1
I/O Devices
Timer 0
McBSP2
UTOPIA:
Up to 400 Mbps
Master ATMC
McBSPs:
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
UTOPIA^(B)
or
McBSP1^(B)
Enhanced
DMA
Controller
(64-channel)
L2
Memory
1024K
Bytes
McBSP0
C64x Digital Signal Processor
L1P Cache
Direct-Mapped
16K Bytes Total
C64x DSP Core
Instruction Fetch
Instruction Dispatch
Advanced Instruction Packet
Instruction Decode
Data Path A
Data Path B
A Register File
A31−A16
A15−A0
B Register File
B31−B16
B15−B0
Control
Registers
Control
Logic
Test
Advanced
In-Circuit
Emulation
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
Interrupt
Control
L1D Cache
2-Way Set-Associative
16K Bytes Total
16
GPIO[8:0]
GPIO[15:9]^(B)
32
HPI^‡
or
PCI^(B)
Interrupt
Selector
PLL
(x1, x6, x12)
Power-Down
Logic
Boot Configuration
A. VCP and TCP decoder coprocessors are applicable to the C6416 device only.
B. For the C6415 and C6416 devices, the UTOPIA peripheral is multiplexed with McBSP1, and the PCI peripheral is
multiplexed with the HPI peripheral and the GPIO[15:9] port. For more details on the multiplexed pins of these
peripherals, see the Device Configurations section of this data manual.
6
Introduction
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